This invention relates to a clock signal detection circuit and, more particularly, to a clock signal detection circuit used to detect interruption of a light signal input in the light receiver of high-speed digital communication system.
The light receiver of a high-speed optical communication system converts a data waveform distorted by transmission or a data waveform distorted by noise to a clean signal waveform. The light receiver performs so-called data and clock regeneration. When data is to be regenerated, the light receiver extracts and regenerates a clock signal from the received data signal and performs the regeneration of the data by a discriminator using the generation timing of the clock signal as a reference.
Such an optical communication system has a variety of fault detection functions for monitoring whether the system is operating normally and discovering faulty points when anomalies occur. Among these functions, one that is for detecting whether a light signal is being received, namely a function for detecting interruption of the light signal, is essential for the light receiver and is required to operate normally in order to find the locations of faults.
FIG. 16 is a block diagram showing the construction of a light receiver in an optical communication system. The light receiver includes a light-receiving element 100 for converting a light signal to an electric signal, an equalizing amplifier circuit 200 for equalizing and amplifying a 10-Gbps data signal, for example, output by the light-receiving element 100, a timing extraction unit 300 for extracting a clock signal, which has a frequency the same as that of the bit rate, from the data signal that has been equalized and amplified, a discriminator 400 for discriminating "1" and "0" logic of the data signal using the clock signal output by the timing extraction unit 300, and a clock signal detector 500 for detecting the amplitude of the clock signal extracted by the timing extraction unit 300. The clock signal detector 500 is capable of detecting interruption of the optical input by comparing the clock signal amplitude and a reference.
In operation, a light signal that has arrived through an optical fiber is converted to an electric signal by the light-receiving element 100. The electric signal is equalized and amplified by the equalizing amplifier circuit 200. The timing extraction unit 300 extracts a clock signal CLK from the equalized waveform to trigger the discriminator 400. The latter determines whether the equalized waveform is indicative of "0" or "1" at the sampling timing, thereby reproducing the original code pulses (data) and outputting the same. Since there is a change in delay time in regard to transmission through the transmission line, a clock signal synchronized to the received data signal is regenerated and the discriminator 400 is triggered by the clock signal.
FIG. 17 is a block diagram showing the construction of the timing extraction unit. The timing extraction unit includes a data edge detector 110 for detecting leading and trailing edges of the data signal, a bandpass filter (BPF) 111, which has a center frequency identical with the bit rate of the data and a characteristic exhibiting a very high Q, which is generally on the order of 1000, and a limiter amplifier 112 for amplifying and shaping the waveform of the BPF output. FIG. 18 is a diagram showing the f characteristic of the BPF 111, where f.sub.0 represents the center frequency of the BPF and .DELTA.f the 3 dB bandwidth of the BPF 111. Accordingly, Q is given by the following: EQU Q=f.sub.o /.DELTA.f
Though the circuits are not shown, the data edge detector 110 includes a branching circuit for branching the data signal in two directions, a delay circuit for delaying, by a prescribed length of time, one of the branched data signals, and an EX-OR (exclusive-OR) circuit for taking the exclusive-OR between the data signal and the output signal of the delay circuit to generate an edge signal having pulses at the leading and trailing edges of the data signal.
FIG. 19 is a waveform diagram showing the operation of the components in the timing extraction unit. The data edge detector 110 generates pulses at the leading and trailing edges of the data signal, the bandpass filter 111 extracts the clock component, which has a frequency identical with the bit rate of the data, from the output of the data edge detector 110, and the limiter amplifier 112 amplifies and shapes the waveform of the clock component.
In parallel with the above-described operation, the clock detector 500 detects the amplitude of the clock signal extracted by the timing extraction unit 300, compares the clock signal amplitude with a reference and outputs a light-input interruption alarm signal if the clock signal amplitude is less than the reference. The S/N ratio of the data signal output by the equalizing amplifier 200 deteriorates if there is a decline in the light input power. If the S/N ratio of the data input signal deteriorates, then the amplitude of the clock signal extracted by the timing extraction unit 300 falls. As a result, the clock signal detector 500 is capable of generating the light-input interruption alarm signal upon detecting the interruption of the light signal by comparing the clock signal amplitude extracted by the timing extraction unit 300 with the reference.
Certain problems arise when detecting the clock signal amplitude. These problems will now be described.
Extraction of the clock signal is performed by coupling the timing extraction unit 300 and the clock signal detector 500 via a capacitor 121, as illustrated in FIG. 20A. Consequently, the clock signal amplitude that can be utilized to detect light input and interruption of the light input becomes half of peak to peak, as shown in FIG. 20B, as a result of which detection efficiency declines. Accordingly, in order detection interruption of the light input and generate an alarm, it is necessary to provide an amplifier capable of high-speed operation and having a high gain. In addition, output linearity (limiter amplitude value) must be improved to assure sufficient amplitude. However, such an amplifier generally is costly and consumes a large amount of power.
Further, an effective method of detecting clock signal amplitude is to regenerate the DC component of the clock signal as in the manner of a diode clamper. With a diode clamper, however, the effects of parasitic capacitance and the like become more pronounced when the clock signal frequency is on the gigahertz order, as a result of which satisfactory direct current regeneration can no longer be performed.
Further, the method of detecting clock signal amplitude generally is a peak detection method using a diode. However, if the bit rate exceeds several gigahertz, bandwidth deterioration occurs owing to the parasitic capacitance of the diode, as a consequence of which detection efficiency declines.